APDR

Computers, Algorithms, and Boolean Logic Lab

Algorithms, Programming, and Data Representation · Module 92313 · Chapter 2

Predict first, then reveal. Work through four short experiments on algorithm steps, Boolean decisions, NAND constructions, and real-circuit timing.

How the lab works

  1. Predict. Commit to an answer before the stage moves.
  2. Rate your confidence. A sure but wrong answer is useful; it appears under Your results.
  3. Watch the reveal. Follow the steps or signal change, then use the link to review the matching guide section.
  4. Explore. Finish an experiment to open its controls and tick its lab skill.

2.1 Square-root algorithm: follow the control flow

For x=16, start at guess g=3. The procedure checks how close g² is to x; if it is not close enough, it replaces g with the average of g and x/g. This sandbox uses a practice tolerance of 0.01.

Practice tolerance: 0.01 · the marker keeps your prediction visible

Try another input

New guess: 3.000 · residual: —

2.4–2.6 Boolean decisions: evaluate the umbrella rule

Let C mean “taking the car”, W mean “bad forecast”, and R mean “raining”. The rule is U=C'·(W+R): take an umbrella when you are not taking the car and either weather condition is true.

1 means true · 0 means false · the output is a stable logic value

Set the propositions

Umbrella U: —

Or try your own

Use C, W, R, 0, 1, + for or, CW or C·W for and, ′ for not and brackets. It is checked against C′·(W+R) on every row.

2.7 NAND gates: build NOT, AND, and OR

NAND combines AND with inversion. Tying both inputs together makes NOT; combining NAND outputs lets you build AND and OR from the same gate type.

A NAND gate outputs 0 only when both inputs are 1

Choose a NAND construction

Output: —

Or try your own

Nest NAND(x, y) with A, B, 0 and 1. The inputs A and B above feed it.

2.8 Physical circuits: compare logic and timing

A truth table tells you the stable output for each input. A real circuit needs time to switch; the time selector uses a symbolic delay Δt because the slides give no measured delay value.

Simplified: the slide shows a gradual change across Δt; here the output jumps at Δt

Explore a one-gate transition

Output at this time: —

Your results

Personal study lab based on the supplied APDR Chapter 2 guide and lecture slides. The timing display uses a symbolic teaching model; it is not a measurement of a physical gate. Not an official FAU publication; check course details against the current materials. Made by Thanate Amornjiraporn (Focus).