Memory Organisation Lab
Algorithms, Programming, and Data Representation · Module 92313 · Chapter 5
Predict first, then reveal. Watch addresses become capacities, chips become modules, and address bits select interleaved memory.
How the lab works
- Predict. Commit before the stage moves.
- Rate confidence. Sure but wrong answers appear first in your results.
- Watch the reveal. Follow the rule behind the answer.
- Explore. Finish all four challenges to open each experiment’s sandbox.
5.1 Memory hierarchy: compare speed and capacity
Compare registers, cache, main memory, and storage across speed, capacity, and volatility.
Registers → cache → RAM → storage.
5.1 SRAM and DRAM: compare cell trade-offs
Trace the cell design, refresh need, speed, density, power, and typical use of each RAM type.
SRAM is fast cache; DRAM is refreshed, dense main memory.
5.2 Addressing: turn bits into capacity
Address width counts locations; the addressed unit determines bytes per location.
2ⁿ locations × bytes per location.
5.3 Endianness: place bytes at addresses
See how big-endian and little-endian layouts place a multi-byte value. A single-byte text sequence keeps its character order.
The byte order changes within each multi-byte value.
5.4 Memory modules: combine chips into capacity
Combine chip widths in parallel, then count rows and modules to calculate system capacity.
Rows × chip width × chips ÷ 8 × module count.
5.5 Interleaving: map addresses to modules
Choose high-order or low-order interleaving, then follow the module bits and row bits.
Low order cycles modules for neighbouring addresses; high order groups address ranges.
Your results
Personal study lab based on the Chapter 5 guide and the supplied “05_memory_organisation.pdf”. Memory capacities use the binary M and G conventions in the lecture where indicated. Not an official FAU publication; check course details against the current notes. Made by Thanate Amornjiraporn (Focus).